WAITEN=WAITEN_0, DOZEEN=DOZEEN_0, FRR=FRR_0, STOPEN=STOPEN_0, ENMOD=ENMOD_0, CLKSRC=CLKSRC_0, IM2=IM2_0, SWR=SWR_0, FO3=FO3_0, EN_24M=EN_24M_0, EN=EN_0, OM3=OM3_0, DBGEN=DBGEN_0
GPT Control Register
| EN | GPT Enable 0 (EN_0): GPT is disabled. 1 (EN_1): GPT is enabled. |
| ENMOD | GPT Enable mode 0 (ENMOD_0): GPT counter will retain its value when it is disabled. 1 (ENMOD_1): GPT counter value is reset to 0 when it is disabled. |
| DBGEN | GPT debug mode enable 0 (DBGEN_0): GPT is disabled in debug mode. 1 (DBGEN_1): GPT is enabled in debug mode. |
| WAITEN | GPT Wait Mode enable 0 (WAITEN_0): GPT is disabled in wait mode. 1 (WAITEN_1): GPT is enabled in wait mode. |
| DOZEEN | GPT Doze Mode Enable 0 (DOZEEN_0): GPT is disabled in doze mode. 1 (DOZEEN_1): GPT is enabled in doze mode. |
| STOPEN | GPT Stop Mode enable 0 (STOPEN_0): GPT is disabled in Stop mode. 1 (STOPEN_1): GPT is enabled in Stop mode. |
| CLKSRC | Clock Source select 0 (CLKSRC_0): No clock 1 (CLKSRC_1): Peripheral Clock (ipg_clk) 2 (CLKSRC_2): High Frequency Reference Clock (ipg_clk_highfreq) 3 (CLKSRC_3): External Clock 4 (CLKSRC_4): Low Frequency Reference Clock (ipg_clk_32k) 5 (CLKSRC_5): Crystal oscillator as Reference Clock (ipg_clk_24M) |
| FRR | Free-Run or Restart mode 0 (FRR_0): Restart mode 1 (FRR_1): Free-Run mode |
| EN_24M | Enable 24 MHz clock input from crystal 0 (EN_24M_0): 24M clock disabled 1 (EN_24M_1): 24M clock enabled |
| SWR | Software reset 0 (SWR_0): GPT is not in reset state 1 (SWR_1): GPT is in reset state |
| IM1 | See IM2 |
| IM2 | IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event 0 (IM2_0): capture disabled 1 (IM2_1): capture on rising edge only 2 (IM2_2): capture on falling edge only 3 (IM2_3): capture on both edges |
| OM1 | See OM3 |
| OM2 | See OM3 |
| OM3 | OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode 0 (OM3_0): Output disconnected. No response on pin. 1 (OM3_1): Toggle output pin 2 (OM3_2): Clear output pin 3 (OM3_3): Set output pin 4 (OM3_4): Generate an active low pulse (that is one input clock wide) on the output pin. |
| FO1 | See F03 |
| FO2 | See F03 |
| FO3 | FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register) 0 (FO3_0): Writing a 0 has no effect. 1 (FO3_1): Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. |